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ЗарегистрироватьсяКандидат
Мужчина, 35 лет, родился 25 июня 1989
Москва, готов к переезду (Зеленоград, Московская область), готов к командировкам
ASIC design engineer
150 000 ₽ на руки
Специализации:
- Инженер-конструктор, инженер-проектировщик
Занятость: полная занятость
График работы: полный день
Опыт работы 14 лет 1 месяц
Июнь 2013 — по настоящее время
11 лет 11 месяцев
Synopsys Inc.
Электроника, приборостроение, бытовая техника, компьютеры и оргтехника... Показать еще
Senior ASIC design engineer
I am responsible for:
RTL creation and standalone RTL level verification of JTAG accessible servers organizing embedded cores test and repair.
Front-end design of IEEE1500 based wrappers, organizing embedded core test and repair using Verilog.
Coverage driven verification and test-bench development.
Development and optimization of TCL based Verilog RTL compilers.
Development of scripts and verification components, for automated design verification ( code coverage, lint etc.)
Сентябрь 2010 — Сентябрь 2012
2 года 1 месяц
Synopsys Inc.
Армения, synopsys.com
Электроника, приборостроение, бытовая техника, компьютеры и оргтехника... Показать еще
ASIC desing engineer RTL Design Group
Worked asa ASIC design engineer Front End.
Design and development of Built-In Self Test and Repair (BIST/BIRA) processors for embedded SRAM, ROM and CAM memories.
Participated in development and verification of various RTL projects.
Participated in development and verification of TCL based compilers for automated generation of Verilog RTL codes.Took part in design and developed the detailed technical specification of STAR Memory System (SMS) for SRAM and ROM memories.
Verified a several releases of SMS compilers.
Август 2010 — Октябрь 2010
3 месяца
VIRAGE LOGIC LLC
Электроника, приборостроение, бытовая техника, компьютеры и оргтехника... Показать еще
R&D engineer, RTL Design Group
Performed functional verification, debugging of RTL modules. Took part in development and Verilog coding of various functional block
Обо мне
Growth-driven engineer with 5+ years of experience in ASIC digital hardware design.
Proficient in RTL coding in Verilog, VHDL, System Verilog, following design rules and guidelines.
Experience in scripting languages including: TCL, Python.
Specialties: ASIC design environment simulation/verification packages:
Verilog HDL, VHDL, System Verilog, TCL, Perl.
VCS, Design Compiler, LEDA Checker, Formality, Prime Time, Hspice, Custom Designer SE/LE, Embed-It, SpyGlass, ModelSim, NC-Verilog.
Platforms: Windows, Unix-like systems.
Высшее образование (Кандидат наук)
2015
National Research University of Electronic Technology, MIET
EDA, EDA
2012
International Scientific - Educational Center of NAS RA, ISEC
Radiocommunication, Masters Degree, “Image de-nosing wavelet algorithms".
2010
Synopsys Armenia Education Department
Very large scale integrated circuits(VLSI), Bachelors Degree, "Design and Investigation of Digital and Analog Lock Detectors".
2010
State Engineering University of Armenia
Electronic technique, Bachelors Degree, "Design and Investigation of Lock Detectors".
Знание языков
Повышение квалификации, курсы
2010
"LA-MARK" TRAINING CENTER
Language Courses: English (intensive), Certificate of graduation the upper-intermediate level
Тесты, экзамены
2012
American University of Armenia (AUA)
The American University of Armenia (AUA) is a U.S.-accredited graduate institution., TOEFL iBT 85.
Гражданство, время в пути до работы
Гражданство: Армения
Разрешение на работу: Россия
Желательное время в пути до работы: Не имеет значения