Разработка SoC / СНК на базе микропроцеcсорного ядра RISC-V.

‣ Chip-Level Physical Verification (Calibre DRC/LVS) of SoC on GF22FDX technology; ‣ Block-level RTL2GDS design of of blocks for a GF22FDX ASIC (Logic Synthesis with Genus CUI, Place-and-Route, CTS, STA with Innovus CUI, Conformal LEC, Tempus Signoff STA, Calibre DRC/LVS);

Выполнение заказных проектов цифровой топологии, консультация крупных европейских чипмейкеров по маршруту RTL-2-GDS. Разработка маршрутов под новые технологии. Обновление существующих маршрутов в соответствии с требованиями новых версий САПР.

Логический синтез, работа с компиляторами памяти, разработка топологии цифровых схем, разработка топологии аналоговых схем

Разработал топологию чипа для майнинга Биткоин и Биткоин Кэш по технологии Samsung LN10LPP (10nm). В рамках разработки проводил логический синтез в Cadence Genus 18 и топологию в Innovus 18, формальную верификация в Conformal. DRC, LVS, LPE, spice и Монте Карло симуляцию схемы с паразитными параметрами. В рамках работы по созданию ASIC разработал топологии заказных логических ячеек: полный-сумматор, половинный сумматор, генератор тактового сигнала с цифровым управлением, заказной 32-разрядный сумматор на CPL логике. В рамках разработки чипа проведены сравнения результатов на технологиях TSMC 16нм, Global Foundries 22nm SOI и 14нм Fin-Fet. Проект приостановлен из-за текущей неопределенности на рынке криптовалют.

Разработал параметризованные ячейки для технологии одной из Зеленоградских фабрик, что позволило ускорить разработку топологии проектируемой схемы. Разрабатывал топологию логических элементов, разрабатывал топологию цифровых блоков на основе разработанных логических элементов. Полностью разработал топологию цифровой схемы коррелятора по технологии 180нм

Лаборатория Инженерной Физики Физического факультета МГУ Консультации по внедрению маршрута RTL2GDS, консультации по выбору метода упаковки проектируемого чипа.

OA library, Technology LEF development frontend development of new device class – stacked ESD MOSes within 40nm PDK

Analog layout development on 180nm high voltage technology with Virtuoso XL, Calibre LVS, DRC, MRC, Tiling. Achievements: Two successful tapeouts.

TechFile, TechLEF development within PDK team. • Technology Database development and support for Freescale and 3rd-pary PDK • Technology LEF development • Maintain consistancy between TechLEF and TechDB • RTL to GDS Flow development, support and testing Achievements: • Deployed Dynamic Abstract capability for Freescale PDKs • Leaded Encounter Tiling development • Integrated cadence PVS with the tiling deck from TSMC into Encounter for 28nm and 16nm processes to allow signoff-quality tiling within Encounter and proper timing assessment. • 4 bug CCR for Cadence Encounter and 2 enhancement request CCR for PVS. • Enabled Voltage aware P&R in Cadence Virtuoso and VSR by Voltage-dependent spacing constraints

Pcell development and unit testing using Skill language. •become familiar with Skill language

• PDK Validation (Cadence IC package both cdba & OA, Soc Encounter, QRC, Voltage Storm, Abstract generator, DRD. Mentor Graphics tools (Calibre DRC, LVS, DRV, PEX). Freescale tools) • Communication with colleagues across the globe: PDK Flow Validation team India, customers and developers in US, Israel. Development of new testing tasks, testing flows and methodologies. • Driving automation: enhancement requests for the automation team, self-made scripts. • Ownership of cmos45soi (45nm), cmos32soi (32nm), TSMC's cln40lp (40nm), cln28hp (28nm) • Leadership over intern colleague: help in team integration, lot of trainings with CAD tools, design flows, methodologies etc. • Leadership over the PDK Validation team during owned PDK's testing: (Creation of Validation Plan, downloading and installing PDK, setting up the environment, tool versions, distribution of the testing tasks across the team, driving meeting the deadline in tight schedule, communication with developers, creating postmortem reports, presentations) • Lead Continuous Validation Improvement program (Analyzing incoming Bug tickets and closure of Validation gaps) • Worked with Physical Verification Team to create DRC and MRC QA cells Achievements: • Input quality control done for cmos32soi, cln28hp and cln40lp 3rd party PDKs allowed proper resource assessment and enabled development activities for Freescale internal PDK solutions • Develop express testing methodology for foundry PDKs • Technology LEF verification on design IP newsletter creation to present PDK Validation team innovations for the entire company • Expertise in parasitic extraction flow • Developed LVS-LPE flow for cln40lp technology • Developed Tiling script for SOC Encounter supplied with Cmos45soi PDK • Developed SOC Encounter automated flow for PDK testing using shell and TCL scripting allowed to reduce testing time • Moscow machines benchmarking methodology was developed and performed • Collaboration with design team - performed preliminary DRC assessment of developing IP on cln40lp technology • Personal “Winning Starts Here” award, Team award for Contribution in the Quality. Passed Cadence trainings: • Virtuoso Connectivity-Driven Layout vIC 6.1.3 (ILS) • Virtuoso Layout Suites L, XL, and GXL (ILS) • Cadence Space-Based Router

iLab • Test flows processing (SOC Encounter, Virtuoso, Assura, PVS, CCO. A variety of tools for IC design automation) • csh and encounter text command scripting (TCL) • Preparation of testcases, writing PCR’s Achievements: • Got familiarity with encounter TCL scripting, • Got familiarity with CVS Versioning system • Got ownership over largest test flow in the team

• Digital and analog layout development (Virtuoso layout editor, Encounter) • Chip-level SOC design, IO cells layout design, digital cells layout design; • Layout verification (Cadence, Mentor Graphics tools DRC, LVS, LPE)

Intel representative in Intel Demo Days activity (Common Intel and Microsoft program. Advertisement of released Pentium 4 CPU's together with Microsoft Windows XP OS, leading of demo-stand in large trading centers of Moscow) Responsibilities: provide potential customers with information about Intel innovative CPU's, presentations and technical demonstrations using various software packages. Provide information about features of released OS, propagate information about advantages of the genuine software. Skills required and demonstrated: • Deep knowledge of IBM PC architecture and hardware • CPU architecture fundamentals • Practical experience with number of software application. • Excellent communication skills.

Электроники и компьютерных технологий, Электроника и микроэлектроника